Error correction method and error correction circuit

ABSTRACT

An error correction method comprises the steps of loading a value stored in a syndrome register (15) to syndrome registers (16) to (18) if error is a single-error after syndrome registers [S0 to S3] (15) to (18) had finished calculating syndromes and loading values stored in the syndrome registers (16) to (18) to data registers [R1 to R3] (22) to (24), repeating multiplications of powers of α, α 2 , α 3  by using the syndrome registers (15) to (18) until coincidence detecting circuits (25) to (28) detect that the values of the syndrome registers (15) to (18) and the values of the data registers (22) to (24) are agreed, energizing a counter (29) in synchronism with the multiplications of powers, setting a count value obtained when it is detected that the values of the syndrome registers and the values of the data registers are agreed to a data location and effecting error correction based on the value of the syndrome register [S0] (15) used as an error amount.

TECHNICAL FIELD

The present invention relates to an error correction method and an errorcorrection circuit and, particularly to an error correction method andan error correction circuit for use in error correction in digital dataprocessing apparatus, such as reproducing apparatus for reproducing a CD(compact disc) and a DAT (digital audio tape) or the like.

BACKGROUND ART

An error correction code of CD is formed by interleaving 2-stageReed-Solomon codes and referred to as CIRC (Cross InterleavedReed-Solomon Code). The 2-stage Reed-Solomon codes used in the CIRC arereferred to as C1, C2, respectively.

When error is corrected by the C1 code, for example, error-correction iscarried out at the unit of 32 byte-data in which 4-byte parity data areadded to 28-byte data. The 32-byte data are referred to as x₀ to x₃₁,respectively.

4-byte parity data are selected such that all of four equations on[Equation 1] yield "0"s: ##EQU1##

Data thus generated are recorded on the disc, and recorded data containserror due to various causes when reproduced.

Data (data containing errors) received by an error correction circuitafter they had been read out from the disc are respectively referred toas x₀ ' to x₃₁ ' in order that they can be distinguished from datarecorded on the disc.

When error correction is implemented in actual practice, data isreceived and then syndromes S0 to S3 are calculated based on [Equation2]: ##EQU2##

Galois field theorem proved that there exists a finite field having 2⁸elements. This finite field is expressed as GF(2⁸).

Codes used in the CD are defined by generator polynomial on [Equation3]:

    P(x)=x.sup.8 +x.sup.4 +x.sup.3 +x.sup.2 +1                 (3)

Then, α is a root of equation established when P(x)=0.

Study of [Equation 2] reveals that, if received data contains no error,then S0=S1=S2=S3=0 (parity data are added for this reason). Conversely,if any one of syndromes were not "0", data error could be detected.

Although the syndrome should be calculated based on the [Equation 2]prior to the error correction, if the syndromes were calculated asdescribed above, then the number of calculation would be increased.

Therefore, [Equation 2] is modified as [Equation 4]: ##EQU3##

The syndrome S1, for example, can be calculated in accordance with analgorithm shown in FIG. 3. Other syndromes S0, S2, S3 also can similarlybe calculated by changing a predetermined power of α variously.

This calculation can be implemented by a circuit composed of an adder 41supplied at one input thereof with received data, a register 42 forstoring added data from the adder 41 and a multiply-by-power α circuit43 for multiplying data stored in the register 42 with power α andsupplying multiplied data to the other input of the adder 41 as shown inFIG. 4.

In FIG. 4, received data are input to the circuit in the sequentialorder from the data x₃₁ ' under the condition that the register 42 isreset. Then, the value that was generated from the register 42 when thedata x₀ ' is input becomes the value of the syndrome S1.

Because the syndromes S0, S2, S3 are required in actual practice, asshown in FIG. 5, the syndromes are calculated by four registers 42₀ to42₃.

The multiply-by-power α circuit 43 and the adder 41 can easily berealized by a combination of exclusive-OR (EX-OR) gates based onfeatures of Galois field as shown in FIGS. 6 and 7.

It is important to detect an error amount prior to the error correction.Also, up to 2-byte error can be corrected in the code used by the CD.

Heretofore, calculation for determining an error amount (0- byte, 1-byteand 2-byte or larger) is carried out after calculation of the syndromeswas finished.

If the received data x_(i) ' is erroneous by an error amount e_(i) ',then the syndromes expressed by [Equation 5] are to be calculated aswill easily be understood from the parity data structure. ##EQU4##

The error amount e_(i) and an erroneous received data location i arecalculated from the syndromes thus calculated.

Since the four equations of [Equation 5] has two unknowns, theseequations can be solved with ease, e.g., based on [Equation 6]: ##EQU5##

However, if received data had 2-byte error or greater, the received datawould be corrected erroneously. Therefore, e^(i) α^(2i) and e_(i) α^(3i)should be calculated by using α^(i) and e_(i) obtained from [Equation5]. Then, it is necessary to confirm whether or not the calculatedresults are agreed with the syndromes S2, S3 of [Equation 5].

As described above, the conventional error correction circuit based onthe above-mentioned algorithm should carry out at least one division andtwo multiplications when 1-byte error is corrected.

These calculations are those that are carried out on the Galois field.Since it is customary that, when the multiplication and the division arecarried out on the Galois field, number to be calculated is modified inthe form of power of α, it is necessary to use a ROM in which a table ofexponents and a table of logarithms for such modification are stored.Moreover, a peripheral circuit becomes complex in circuit arrangementand a circuit scale is unavoidably increased.

DISCLOSURE OF INVENTION

In view of the aforesaid problem, it is an object of the presentinvention to provide an error correction method and an error correctioncircuit in which error detection and error correction can be realized bya circuit arrangement of an extremely small circuit scale.

According to a first aspect of the present invention, there is providedan error correction method which comprises the steps of calculating n (nis a positive integer) syndromes determined by the number of parity dataadded to received data from the received data, storing a syndromerepresenting an error amount of a single-error, if error is thesingle-error, in a single syndrome register and storing other syndromesin (n-1) syndrome registers, respectively, loading a value stored in thesingle syndrome register to the (n-1) syndrome registers and loadingrespective values stored in the (n-1) syndrome registers to (n-1) dataregisters, respectively, after calculation of the syndromes was ended,repeating multiplications of powers of α, . . . , α.sup.(n-1) by usingthe (n-1) syndrome registers where α is a root of generator polynomialon the Galois field until it is detected that the values stored in the(n-1) syndrome registers and the values stored in the (n-1) dataregisters are agreed with each other, effecting counting in synchronismwith the multiplication of powers, setting a count value obtained whenthe values are agreed with each other to a location of data containingerror and setting the value stored in the single syndrome register to anerror amount, and effecting error correction based on the data locationand the error amount. The syndromes are calculated by syndrome registersS0, S1 to S(n-1). After the syndrome registers have finished calculatingthe syndromes, if error is a single-error, the value stored in thesyndrome register S0 is loaded to the syndrome registers S1 to S(n-1),and values stored in the syndrome registers S1 to S(n-1) are loaded todata registers R1 to R(n-1), respectively. Multiplications of powers ofα, . . . , α.sup.(n-1) are repeated by using the syndrome registers S1to S(n-1) until the values stored in the syndrome registers S1 to S(n-1)and the values stored in the data registers R1 to R(n-1) are agreed witheach other, and count operation is effected in synchronism with themultiplications of powers. Thus, a count value obtained when it isdetected that the values of the registers S1 to S(n-1) and the values ofthe data registers R1 to R(n-1) are agreed is set to a location of datacontaining error and an amount of error becomes a value of the syndromeS0.

According to a second aspect of the present invention, there is providedan error correction circuit using the error correction method accordingto the first aspect of the present invention. The error correctioncircuit comprises a syndrome register group composed of a singlesyndrome register for calculating syndromes from received data andstoring a syndrome representing an error amount of a single-error iferror is the single-error and (n-1) syndrome registers for storing othersyndromes, (n-1) data registers for holding values stored in the (n-1)syndrome registers, coincidence detecting circuits for detecting whetheror not the values stored in the (n-1) syndrome registers and the valuesstored in the (n-1) data registers are agreed with each other, and acounter being energized in synchronism with the multiplications ofpowers and being disabled in response to detected outputs from thecoincidence detecting circuits, wherein error-correction is carried outbased on a count value of the counter and the value stored in the singlesyndrome register. Thus, a single-error (1-byte error) can be detectedand corrected by a circuit arrangement of an extremely small circuitscale composed of n syndrome registers necessary for calculatingsyndromes, (n-1) data registers, one counter and the coincidencedetecting circuits, each of which is added to the syndrome registers.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing an error correction circuit accordingto an embodiment of the present invention;

FIG. 2 is a flowchart of an error correction algorithm according to thepresent invention;

FIG. 3 is a flowchart of a calculation algorithm of syndrome S1;

FIG. 4 is a block diagram showing an example of a calculation circuitfor calculating syndrome S1;

FIG. 5 is a block diagram showing an example of a calculation circuitfor calculating syndromes S0 to S4;

FIG. 6 is a block diagram showing an example of a multiply-by-power αcircuit; and

FIG. 7 is a block diagram showing an example of an adder which carriesout addition on the Galois field.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be described below in detailwith reference to the drawings.

FIG. 1 is a block diagram showing an error correction circuit accordingto an embodiment of the present invention.

In FIG. 1, received data RD is supplied to each one input of four adders11 to 14. Respective added data from these adders 11 to 14 are stored infour syndrome registers [S0 to S3] 15 to 18 that are used to calculatesyndromes S0 to S3. The syndrome registers 15 to 18 are operated insynchronism with a clock CK supplied thereto.

Respective data stored in the syndrome registers [S1 to S3] 16 to 18 ofthe four syndrome registers 15 to 18 are supplied through amultiply-by-power α circuit 19, a multiply-by-power α² circuit 20, amultiply-by-power α³ circuit 21 to other inputs of the adders 12, 13, 14and also stored in three data registers [R1 to R3] 22 to 24,respectively.

Respective data stored in the data registers [R1 to R3] 22 to 24 aresupplied to each one of inputs of three logic gates 25 to 27.

These logic gates 25 to 27 are supplied at their other inputs withrespective data stored in the syndrome registers [S1 to S3] 16 to 18 andgo to logic "1" level when logic values of respective corresponding bitsof the two sets of registers are all agreed. Respective outputs of thelogic gates 25 to 27 are supplied to respective inputs of a 3-input ANDgate 28.

The AND gate 28 goes to logic "1" level when the input levels are all atlogic "1" level, i.e., the outputs of the logic gate 25 to 27 are allagreed.

A counter 29 is adapted to count the same clock CK as those supplied tothe four syndrome registers 15 to 18. The counter 29 is reset anddisabled under the control of a CPU 30.

Specifically, when the number (location) i of erroneous data containedin received data and an error amount e_(i) of the received data arecalculated from the syndromes S0 to S3 thus obtained, the counter 29 isreset to "0"and disabled when the AND gate 28 detects that the levels ofthe logic gates are all agreed.

At the completion of the error calculation, the value stored in the S0register 15 at that very ending time point becomes the error amounte_(i) and the count value j of the counter 29 becomes the number(location) i of erroneous data. Then, received data of the errorlocation i stored in a buffer memory, not shown, is accessed to thereceived data input unit shown in FIG. 1 and thereby added with the datastored in the S0 register 15.

When such processing is carried out at the completion of thecalculation, data that had been error-corrected is left in the S0register 15. Then, error-corrected data DT is output and the errorcorrection is completed.

The algorithm according to the present invention will be described nextwith reference to a flowchart of FIG. 2.

Initially, syndromes are calculated by the adders 11 to 14, the syndromeregisters [S0 to S3] 15 to 18, the multiply-by-power α circuit 19, themultiply-by-power α² circuit 20 and the multiply-by-power α³ circuit 21(at step S1).

Assuming now that ith received data, for example, is erroneous by theamount e_(i), then [Equation 5] yields S0=e_(i), S1=e_(i) α^(i),S2=e_(i) α^(1i) and S3=e_(i) α^(3i).

Then, respective data stored in the syndrome registers {S1 to S3] 16 to18 are stored in data registers [R1 to R3] 22 to 24 and data stored inthe syndrome register [S0] 15 is stored in the syndrome registers [S1 toS3], respectively (at step S2).

Therefore, values of the syndrome registers [S0 to S3] 15 to 18 areS0=S1=S2=S3=e_(i), R1=e_(i) α^(i), R2=e_(i) α²¹, R3=e_(i) α^(3i).

Subsequently, the counter 29 is reset to "0" (at step S3), and it isdetermined whether or not S1=R1, S2=R2, S3=R3 are established in thesyndrome registers 16 to 18 and the data registers 22 to 24 (at stepS4).

If 0th received data (x₀ ') is erroneous, then the above-mentioned threeconditions in the S registers and the R registers are all agreed.

If the received data is not erroneous, then the above-mentionedconditions also are established. In this case, since S0=0, it can bedetermined whether or not the received data is erroneous, as will bedescribed later on.

If it is determined in step S4 that the above-mentioned conditions arenot established, so long as j≦31 is established (at step S5), α. S1→S1,α² . S2→S2, α³ . S3→S3 are calculated (at step S6). Then, the countvalue j of the counter 29 is incremented by one (step S7), and theprocess ing returns to step S4.

Calculations in step S6 can be realized only by inputting "0" asreceived data.

As a result of this calculation, the values of the syndrome registers 16to 18 are S1=αe_(i), S2=α² e_(i), S3=α³ e_(i).

It is determined one more time whether or not the conditions, S1=R1,S2=R2, S3=R3 are established (at step S4).

If the first (x₁ ') data of the received data is erroneous, then theseconditions should be established. If these conditions are notestablished, steps S6 and S7 are executed one more time.

If calculation is carried out j times, then the syndrome registers 16 to18 generate S1=α^(j) e_(i), S2=α^(2j) e_(i), S3=α^(3j) e_(i). When j isagreed with i (number of erroneous received data), S1=R1, S2=R2, S3=R3.

Specifically, such calculation is repeated several times. When it isdetermined in step S4 that S1=R1, S2=R2, S3=R3 are established, so longas the condition, S1≠0 is established (step S8), the count value j ofthe counter 29 is set to the number of erroneous data, and the erroramount is set to the value of the syndrome register [S0] 15 (at stepS9).

If S0=0 in step S8, then it is determined that received data contains noerror (at step S10).

If it is determined in step S5 that the S register and the R registerare not agreed with each other even though the count value j of thecounter 29 exceeds 31, then it is determined that received data contains2-byte error or greater. Then, such received data is treated as datathat cannot be corrected (at step S11).

As set out in detail, according to the embodiment of the presentinvention, the syndromes are calculated by the syndrome registers S0, S1to S(n-1). After the syndrome registers had finished calculating thesyndromes, if error is the single-error, then the value of the syndromeregister S0 is loaded to the syndrome registers S1 to S(n-1) and thevalues of the syndrome registers S1 to S(n-1) are loaded to the dataregisters R1 to R(n-1), respectively. Multiplications of powers α, . . ., α.sup.(n-1) are repeated by using the syndrome registers S1 to S(n-1)until the values of the syndrome registers S1 to S(n-1) and the valuesof the data registers R1 to R(n-1) are agreed. Count operation isexecuted in synchronism with the multiplications of powers. The countvalue obtained when it is detected that the values of the syndromeregisters and the values of the data registers are agreed is set to thelocation of data containing error and the value of the syndrome registerS0 is set to the error amount. Then, error correction is carried out onthe basis of the location and the error amount. Therefore, thesingle-error can be detected and corrected by the circuit arrangement ofthe extremely small circuit scale composed of n syndrome registersindispensable to calculation of syndromes, (n-1) data registers, onecounter and coincidence detecting circuits, each of which is added tothe syndrome registers.

While the present invention is applied to the apparatus for reproducingthe CD with the signal format having four syndromes (S0 to S3) asdescribed above, the present invention is not limited thereto and can beapplied to the whole field of digital data processing apparatus. By wayof example, when the present invention is applied to a reproducingapparatus for reproducing a DAT with a signal format having sixsyndromes, error can be detected and corrected similarly as describedabove by increasing the number of syndrome registers and data registersin response to the number of syndromes.

What is claimed is:
 1. A method for correcting errors present in datareproduced from a recording medium comprising the steps of:calculating nsyndromes, wherein n is a positive integer, determined by a number ofparity words added to said reproduced data and storing in a firstsyndrome register a syndrome representing an error amount present insaid reproduced data if said error amount comprises a single-error andstoring other syndromes in (n-1) syndrome registers, respectively, said(n-1) syndrome registers not including said first syndrome register;loading a value stored in said first syndrome register in said (n-1)syndrome registers and values stored in said (n-1) syndrome registers in(n-1) data registers, respectively, after calculation of syndromes isended; repetitively multiplying the values stored in said (n-1) syndromeregisters by a corresponding plurality of multiplication factors, saidplurality of multiplication factors ranging from a factor of α to afactor of α.sup.(n-1), until the respective values stored in said (n-1)syndrome registers and the respective values stored in said (n-1) dataregisters are equal, wherein α is a root of a generator polynomial onGalois field and executing a count operation in synchronism with saidrepetitive multiplying step in which a count value is incremented by apredetermined amount for every multiplying step; designating said countvalue as a data location of said errors present in said reproduced datawhen the values of said (n-1) syndrome registers and the values of said(n-1) data registers are equal and designating the value stored in saidfirst syndrome register as said error amount; and correcting said errorson the basis of said data location and said error amount.
 2. The methodof claim 1, wherein n equals
 4. 3. The method of claim 2, wherein saidrecording medium is a compact disc.
 4. The method of claim 1, wherein nequals
 6. 5. The method of claim 4, wherein said recording medium is adigital audio tape.
 6. An error correction circuit for correcting errorspresent in data reproduced from a recording medium comprising:n syndromeregisters, wherein a first of said n syndrome registers calculates andstores a first syndrome from said reproduced data, said first syndromerepresenting an error amount of a single-error present in saidreproduced data, and wherein (n-1) syndrome registers calculates andstores (n-1) syndromes, said (n-1) syndrome registers not including saidfirst of said n syndrome registers and said (n-1) syndromes notincluding said first syndrome; (n-1) data registers, in communicationwith said (n-1) syndrome registers, for storing values stored in said(n-1) syndrome registers; (n-1) coincidence detecting circuits, incommunication with said (n-1) syndrome registers and in communicationwith said (n-1) data registers, for detecting whether or not the valuesstored in said (n-1) syndrome registers and the values stored in said(n-1) data registers are equal; and (n-1) multiplication circuits, incommunication with said (n-1) syndrome registers and in communicationwith said (n-1) coincidence detecting circuits, for repetitivelymultiplying the values stored in said (n-1) syndrome registers by acorresponding plurality of multiplication factors until the valuesstored in said (n-1) syndrome registers and the values stored in said(n-1) data registers are equal, said plurality of multiplication factorsranging from a factor of α to a factor of α.sup.(n-1), wherein α is aroot of a generator polynomial on Galois field; a counter, incommunication with said (n-1) multiplication circuits and incommunication with said (n-1) coincidence detecting circuits, forincrementing a count value by a predetermined amount until the valuesstored in said (n-1) syndrome registers and the values stored in said(n-1) data registers are equal, wherein said errors present in saidreproduced data are corrected on the basis of said count value of saidcounter and on the basis of said first syndrome.
 7. The error correctioncircuit of claim 6, wherein n equals
 4. 8. The error correction circuitof claim 7, wherein said recording medium is a compact disc.
 9. Theerror correction circuit of claim 2, wherein n equals
 6. 10. The errorcorrection circuit of claim 9, wherein said recording medium is adigital audio tape.